The SRAM (static random access memory), which is a memory cell, is widely applied in the personal communications or consumer electronics with its characteristic of high speed and low power consumption.
As shown in FIG. 1, a conventional 6T SRAM cell is structurally symmetrical, which is consist of six transistors M1, M2, M3, M4, M5 and M6. Wherein, the transistors M1, M2 M3 and M4 form a bi-stable circuit to latch a digital signal. The transistors M5 and M6 are Pass-Gate transistors to connect or disconnect the SRAM cell with the peripheral circuit in the read/write or store operation of the SRAM cell.
During the read operation, the word line WL is enabled to a high potential, and the Pass-Gate transistors are turned on to transfer the digital signal (0 or 1) to the bit line BL and the complementary digital signal (1 or 0) to the bit line BL, then the peripheral circuit will read the data from the bit line BL, BL. During the write operation, the word line WL is enabled to a high potential and the Pass-Gate transistors are turned on, the peripheral circuit transfers the voltage digital signal to the bit line BL, BL, so as to write the digital signal (digital data) in the SRAM cell.
According to the SRAM cell manufacturing process currently, with the decrease of the minimum supply voltage (Vmin), the mismatch between the transistors in the SRAM cell occurs more frequently, and thus decrease the product yield. Therefore, fast and reliable detection of the mismatched (or failed) transistors in the SRAM cell makes the key point for the process development. The detection method today mainly utilizes accurate positioning means and measuring devices such as Nano-prober/AFP to detect and find the mismatched transistors. However, such method is time-consuming, costly, and inconvenient for mass data collection.
Therefore, it is necessary to provide a new mismatch detecting method for the transistors in a SRAM cell.